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risc-v32
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Implementation of a circular linked list in RISC-V. Developed with Ripes (v.2.2.6) for a 32 bit 5 stages processor.
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Sep 20, 2023 - Assembly
Processes a single 32-bit instruction in one single clock cycle. Based on the RISV-32 ISA supporting addition, subtraction, bitwise AND & OR operations.
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Updated
May 21, 2025 - Verilog
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