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Author: patel-soham

pattern.v

@@ -0,0 +1,128 @@
+module pattern(clk, rst, valid, in, out);
+parameter RST=3'b000,
+		  S1=3'b001,
+		  S10=3'b010,
+		  S101=3'b011,
+		  S1011=3'b100,
+		  S10110=3'b101;
+
+input clk, rst, valid, in;
+output reg out;
+
+reg [2 : 0] cs, ns;
+
+
+// Here cs and ns are same values as they move together
+/*always @ (posedge clk) begin
+	if (rst == 1) begin
+		out = 0;
+		cs = RST;
+		ns = RST;
+	end
+	else begin
+		if (valid == 1) begin
+		out = 0;
+			case (cs)
+				RST: begin
+					if (in == 1) ns = S1;
+					else ns = RST;
+				end
+				S1: begin
+					if (in == 1) ns = S1;
+					else ns = S10;
+				end
+				S10: begin
+					if (in == 1) ns = S101;
+					else ns = RST;
+				end
+				S101: begin
+					if (in == 1) ns = S1011;
+					else ns = S10;
+				end
+				S1011: begin
+					if (in == 1) ns = S1;
+					// for Moore
+					//else ns = S10110;
+					// for Melay
+					else begin
+						ns = RST;
+						out = 1;
+					end
+				end
+				// remove this state for Melay
+				/*S10110: begin
+					out = 1;
+					if (in == 1) ns = S1;
+					else ns = RST;
+				end
+            	default: begin
+					ns = RST;
+					out = 0;
+				end
+			endcase
+		end
+		else begin
+			out = 0;
+		end
+	end
+end
+
+always @ (ns) cs = ns;
+*/
+
+// The above code works same as below without even using ns
+always @ (posedge clk) begin
+	if (rst == 1) begin
+		out = 0;
+		cs = RST;
+	end
+	else begin
+		if (valid == 1) begin
+		out = 0;
+			case (cs)
+				RST: begin
+					if (in == 1) cs = S1;
+					else cs = RST;
+				end
+				S1: begin
+					if (in == 1) cs = S1;
+					else cs = S10;
+				end
+				S10: begin
+					if (in == 1) cs = S101;
+					else cs = RST;
+				end
+				S101: begin
+					if (in == 1) cs = S1011;
+					else cs = S10;
+				end
+				S1011: begin
+					if (in == 1) cs = S1;
+					// for Moore
+					//else cs = S10110;
+					// for Melay
+					else begin
+						cs = RST;
+						out = 1;
+					end
+				end
+				// remove this state for Melay
+				/*S10110: begin
+					out = 1;
+					if (in == 1) cs = S1;
+					else cs = RST;
+				end*/
+            	default: begin
+					cs = RST;
+					out = 0;
+				end
+			endcase
+		end
+		else begin
+			out = 0;
+		end
+	end
+end
+
+endmodule
+

pattern1.v

@@ -0,0 +1,100 @@
+module pattern(clk, rst, valid, in, out);
+parameter RST=3'b000,
+		  S1=3'b001,
+		  S10=3'b010,
+		  S101=3'b011,
+		  S1011=3'b100,
+		  S10110=3'b101;
+
+input clk, rst, valid, in;
+output out;
+
+reg [2 : 0] cs, ns;
+
+// For Moore
+//assign out = (cs == S10110) ? 1 : 0;
+//OR
+/*reg out;
+always @ (cs) begin
+	case (cs)
+		RST: out = 0;
+		S1: out = 0;
+		S10: out = 0;
+		S101: out = 0;
+		S1011: out = 0;
+		S10110: out = 1;
+	endcase
+end*/
+
+always @ (posedge clk) begin
+	if (rst == 1) cs <= RST;
+	else cs <= ns;
+end
+
+// For Melay
+// the below assign statements will cause spikes of out on unwanted situations 
+// also output will be observed on same cycle
+//assign out = (cs==S1011 && in==0) ? 1 : 0;
+// OR
+// This works best and output will be on next cycle like normal
+// also this will have no unwanted spikes of out
+reg out;
+always @ (posedge clk) begin // do not keep cs, in in sensitivity list
+// that will also result in spikes before posedge of clk and output will be on same cycle
+	if (cs==S1011 && in==0) out <= 1;
+	else out <= 0;
+end
+// Best for Melay combined
+/*always @ (posedge clk) begin
+	if (rst == 1) begin
+		cs <= RST;
+		out <= 0;
+	end
+	else begin 
+		cs <= ns;
+		out <= (cs==S1011 && in==0) ? 1 : 0;
+	end
+end
+*/
+always @ (cs, in) begin
+	if (valid == 1) begin
+	case (cs)
+		RST: begin
+			if (in == 1) ns = S1;
+			else ns = RST;
+		end
+		S1: begin
+			if (in == 1) ns = S1;
+			else ns = S10;
+		end
+		S10: begin
+			if (in == 1) ns = S101;
+			else ns = RST;
+		end
+		S101: begin
+			if (in == 1) ns = S1011;
+			else ns = S10;
+		end
+		S1011: begin
+			if (in == 1) ns = S1;
+			// For Moore
+			//else ns = S10110;
+			// For Melay 
+			else ns = RST;
+		end
+		// Remove for Melay
+		/*S10110: begin
+			if (in == 1) ns = S1;
+			else ns = RST;
+		end*/
+		default: begin
+			ns = RST;
+		end
+	endcase
+	end
+	else begin
+			ns = RST;
+	end
+end
+
+endmodule

run.do

@@ -0,0 +1,5 @@
+vlib work
+vlog tb_pattern.v
+vsim tb
+add wave sim:/tb/dut/*
+run -all

tb_pattern.v

@@ -0,0 +1,30 @@
+//`include "pattern.v"
+`include "pattern1.v"
+
+module tb;
+
+reg clk, rst, valid, in;
+wire out;
+
+pattern dut (.clk(clk), .rst(rst), .valid(valid), .in(in), .out(out));
+
+always #1 clk = ~clk;
+
+initial begin
+	clk = 0;
+	rst = 1;
+	valid = 0;
+	in = 0;
+	repeat (5) @ (posedge clk);
+	rst = 0;
+
+	valid = 1;
+	repeat (400) @ (posedge clk) begin
+		in = $random;
+	end
+	
+
+	$finish;
+end
+
+endmodule