Linear Feedback Shift Register

A VHDL specification of an LSFR used to produce a pseudo-random sequence of bits.

Assignement

This project has been developed for the Electronics and Communication Systems course (MSc Computer Engineering) at University of Pisa. The project consists in the development of a VHDL specification and implementation on the ZyBo Board by Xilinx of a Linear Feedback Shift Register.

Tools

• The ModelSim - Intel® FPGA edition software - For VHDL implementation and hardware testbranch
• Vivado Design Suite - For the FPGA implementation