- 🙏 Greetings, I’m @UjvalMadhu
- 👀 I’m an Electrical Engineer working in the realm of Digital Systems; this includes Custom ASICs, FPGAs, CPUs, GPUs, and complex SoCs
- 🌱 I’m currently building my expertise in digital systems design and verification + tinkering with the design of Artificial Intelligence Systems
- 💞️ I want to collaborate with individuals on projects that help me learn new and challenging concepts.
- 📫 How to reach me: [email protected]
- Website: https://ujvalmadhu.github.io/UjvalMadhuWeb.github.io/
I am using this space to share, learn, and collaborate with other passionate individuals. I post repos that consist of the projects that I do while trying to learn new concepts. I try to make them as beginner-friendly as possible so that anyone on a similar path can easily use them.
My current major projects are listed here:
Sl No. | Project | Description |
---|---|---|
1. | RTL_Development | This repo contains Synthesizable RTL Design Projects using Verilog, VHDL and SV |
2. | Verification_Projects | This repo contains design verification projects using SV, UVM, and Python Frameworks |
3. | C Projects | This repo contains C and C++ projects |
4. | Python Projects | This repo contains python projects |
5. | RISC-V Projects | This repo consists of projects exploring RISC-V cores |
If you need any help or have questions or suggestions, feel free to reach out through email.
Thank you for visiting, Peace !!!