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drivers: pinctrl: Support pinctrl driver for Renesas RX
Intial support of pinctrl driver for Renesas RX MCU family. This support base on using Renesas RX driver package in hal_renesas layer Signed-off-by: Duy Nguyen <[email protected]> Signed-off-by: Phi Tran <[email protected]>
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‎drivers/pinctrl/renesas/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RX rx/pinctrl_renesas_rx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RZ rz/pinctrl_renesas_rz.c)

‎drivers/pinctrl/renesas/rx/Kconfig

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_RENESAS_RX
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bool "Renesas RX series pin controller driver"
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default y
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depends on DT_HAS_RENESAS_RX_PINCTRL_ENABLED
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select USE_RX_RDP_MPC
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select USE_RX_RDP_GPIO
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help
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Enable Renesas RX series pin controller driver.

‎drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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/* Renesas FIT module for iodefine.h data structures */
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#include "platform.h"
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#include "r_gpio_rx_if.h"
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#include "r_mpc_rx_if.h"
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#define PORT_POS (8)
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extern const uint8_t g_gpio_open_drain_n_support[];
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extern const uint8_t g_gpio_pull_up_support[];
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extern const uint8_t g_gpio_dscr_support[];
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static bool gpio_pin_function_check(uint8_t const *check_array, uint8_t port_number,
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uint8_t pin_number)
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{
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if ((check_array[port_number] & (1 << pin_number)) != 0) {
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return true;
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} else {
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return false;
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}
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}
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static int pinctrl_configure_pullup(const pinctrl_soc_pin_t *pin, uint32_t value)
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{
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gpio_port_pin_t port_pin;
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bool pin_check;
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int ret = 0;
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port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
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pin_check = gpio_pin_function_check(g_gpio_pull_up_support, pin->port_num, pin->pin_num);
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if (pin_check) {
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ret = R_GPIO_PinControl(port_pin, (value ? GPIO_CMD_IN_PULL_UP_ENABLE
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: GPIO_CMD_IN_PULL_UP_DISABLE));
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}
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return ret;
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}
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static int pinctrl_configure_dscr(const pinctrl_soc_pin_t *pin, uint32_t value)
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{
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gpio_port_pin_t port_pin;
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bool pin_check;
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int ret = 0;
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port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
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pin_check = gpio_pin_function_check(g_gpio_dscr_support, pin->port_num, pin->pin_num);
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if (pin_check) {
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ret = R_GPIO_PinControl(port_pin,
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(value ? GPIO_CMD_DSCR_ENABLE : GPIO_CMD_DSCR_DISABLE));
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}
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return ret;
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}
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static int pinctrl_configure_opendrain(const pinctrl_soc_pin_t *pin, uint32_t value)
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{
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gpio_port_pin_t port_pin;
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bool pin_check;
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int ret = 0;
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port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
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pin_check =
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gpio_pin_function_check(g_gpio_open_drain_n_support, pin->port_num, pin->pin_num);
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if (pin_check) {
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ret = R_GPIO_PinControl(
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port_pin, (value ? GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN : GPIO_CMD_OUT_CMOS));
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}
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return ret;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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gpio_port_pin_t port_pin;
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mpc_config_t pconfig = {
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.pin_function = 0x0,
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.irq_enable = false,
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.analog_enable = false,
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};
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int ret;
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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const pinctrl_soc_pin_t *pin = &pins[i];
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port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
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/* Set PMR register to 0 before setting pin control register */
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ret = R_GPIO_PinControl(port_pin, GPIO_CMD_ASSIGN_TO_GPIO);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Set output high */
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if (pin->cfg.output_high) {
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R_GPIO_PinWrite(port_pin, GPIO_LEVEL_HIGH);
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}
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/* Set port direction */
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if (pin->cfg.output_enable) {
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R_GPIO_PinDirectionSet(port_pin, GPIO_DIRECTION_OUTPUT);
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}
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/* Set pull-up */
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ret = pinctrl_configure_pullup(pin, pin->cfg.bias_pull_up);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Set open-drain */
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ret = pinctrl_configure_opendrain(pin, pin->cfg.drive_open_drain);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Set drive-strength */
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ret = pinctrl_configure_dscr(pin, pin->cfg.drive_strength);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Set pin function */
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pconfig.analog_enable = pin->cfg.analog_enable;
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pconfig.pin_function = pin->cfg.psels;
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ret = R_MPC_Write(port_pin, &pconfig);
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if (ret != 0) {
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return -EINVAL;
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}
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/* Set MODE */
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if (pin->cfg.pin_mode) {
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ret = R_GPIO_PinControl(port_pin, GPIO_CMD_ASSIGN_TO_PERIPHERAL);
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if (ret != 0) {
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return -EINVAL;
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}
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}
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}
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return 0;
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}

‎dts/bindings/pinctrl/renesas,rx-pinctrl.yaml

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: |
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description: |
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The Renesas RX pin controller is a node responsible for controlling
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pin function selection and pin properties
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The node has the 'pinctrl' node label set in your SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the
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'pinctrl' node, as shown in this example:
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/* You can put this in places like a board-pinctrl.dtsi file in
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* your board directory, or a devicetree overlay in your application.
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*/
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/* include pre-defined combinations for the SoC variant used by the board */
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#include <dt-bindings/pinctrl/renesas/rx-pinctrl.h>
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&pinctrl {
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sci1_default: sci1_default {
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group1 {
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psels = <RX_PSEL(RX_PSEL_SCI_1, 2, 6)>; /* TX */
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drive-strength = "medium";
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};
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group2 {
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psels = <RX_PSEL(RX_PSEL_SCI_1, 3, 0)>; /* RX */
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drive-strength = "medium";
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};
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};
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};
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The 'sci1_default' child node encodes the pin configurations for a
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particular state of a device; in this case, the default (that is, active)
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state.
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As shown, pin configurations are organized in groups within each child node.
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Each group can specify a list of pin function selections in the 'psels'
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property.
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A group can also specify shared pin properties common to all the specified
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pins, such as the 'input-enable' property in group 2. Here is a list of
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supported standard pin properties:
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- bias-disable: Disable pull-up/down (default, not required).
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- bias-pull-up: Enable pull-up resistor.
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- input-enable: Enable input from the pin.
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- drive-strength: Set the drive strength of the pin. Possible
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values are: normal, high.
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To link pin configurations with a device, use a pinctrl-N property for some
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number N, like this example you could place in your board's DTS file:
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#include "board-pinctrl.dtsi"
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&sci1 {
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pinctrl-0 = <&uart0_default>;
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pinctrl-1 = <&uart0_sleep>;
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pinctrl-names = "default", "sleep";
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};
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compatible: "renesas,rx-pinctrl"
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include: base.yaml
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child-binding:
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description: |
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Definitions for a pinctrl state.
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child-binding:
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-disable
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- bias-pull-up
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- input-enable
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- output-enable
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- output-high
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- drive-open-drain
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properties:
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psels:
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required: true
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type: array
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description: |
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An array of pins sharing the same group properties. Each
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element of the array is an integer constructed from the
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pin number and the alternative function of the pin.
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drive-strength:
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type: string
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enum:
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- "normal"
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- "high"
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default: "normal"
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description: |
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The drive strength of a pin. The default value is normal, as this
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is the power on reset value.
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renesas,analog-enable:
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type: boolean
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description: enable analog input

‎dts/bindings/pinctrl/renesas,rx-pinmux.yaml

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Rensas RX Pinmux (Multi Function Pin Controller, MPC)
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compatible: "renesas,rx-pinmux"
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include: base.yaml
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properties:
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reg:
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required: true
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"#pinmux-cells":
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type: int
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required: true
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const: 2
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description: number of items in a pinmux specifier
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pinmux-cells:
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- pin
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- function
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child-binding:
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include: pincfg-node.yaml

‎dts/rx/renesas/rx130-common.dtsi

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#include <mem.h>
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#include <zephyr/dt-bindings/clock/rx_clock.h>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h>
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/ {
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#address-cells = <1>;

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