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vknechtvknecht
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arm64: dts: qcom: msm8939: Add camss and cci
Add the camera subsystem and CCI used to interface with cameras on the Snapdragon 615. Signed-off-by: Vincent Knecht <[email protected]>
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‎arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi

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@@ -11,6 +11,10 @@
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#include "msm8939.dtsi"
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#include "pm8916.dtsi"
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&camss {
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vdda-supply = <&pm8916_l2>;
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};
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&mdss_dsi0 {
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vdda-supply = <&pm8916_l2>;
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vddio-supply = <&pm8916_l6>;

‎arch/arm64/boot/dts/qcom/msm8939.dtsi

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};
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};
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camss: camss@1b0ac00 {
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compatible = "qcom,msm8939-camss";
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reg = <0x01b0ac00 0x200>,
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<0x01b00030 0x4>,
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<0x01b0b000 0x200>,
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<0x01b00038 0x4>,
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<0x01b08000 0x100>,
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<0x01b08400 0x100>,
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<0x01b08800 0x100>,
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<0x01b0a000 0x500>,
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<0x01b00020 0x10>,
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<0x01b10000 0x1000>,
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<0x01b40000 0x200>;
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reg-names = "csiphy0",
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"csiphy0_clk_mux",
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"csiphy1",
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"csiphy1_clk_mux",
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"csid0",
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"csid1",
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"csid2",
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"ispif",
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"csi_clk_mux",
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"vfe0",
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"vfe0_vbif";
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interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy0",
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"csiphy1",
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"csid0",
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"csid1",
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"csid2",
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"ispif",
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"vfe0";
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power-domains = <&gcc VFE_GDSC>;
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clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
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<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
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<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
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<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
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<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
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<&gcc GCC_CAMSS_CSI0_CLK>,
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<&gcc GCC_CAMSS_CSI0PHY_CLK>,
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<&gcc GCC_CAMSS_CSI0PIX_CLK>,
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<&gcc GCC_CAMSS_CSI0RDI_CLK>,
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<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
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<&gcc GCC_CAMSS_CSI1_CLK>,
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<&gcc GCC_CAMSS_CSI1PHY_CLK>,
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<&gcc GCC_CAMSS_CSI1PIX_CLK>,
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<&gcc GCC_CAMSS_CSI1RDI_CLK>,
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<&gcc GCC_CAMSS_CSI2_AHB_CLK>,
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<&gcc GCC_CAMSS_CSI2_CLK>,
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<&gcc GCC_CAMSS_CSI2PHY_CLK>,
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<&gcc GCC_CAMSS_CSI2PIX_CLK>,
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<&gcc GCC_CAMSS_CSI2RDI_CLK>,
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<&gcc GCC_CAMSS_AHB_CLK>,
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<&gcc GCC_CAMSS_VFE0_CLK>,
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<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
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<&gcc GCC_CAMSS_VFE_AHB_CLK>,
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<&gcc GCC_CAMSS_VFE_AXI_CLK>;
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clock-names = "top_ahb",
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"ispif_ahb",
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"csiphy0_timer",
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"csiphy1_timer",
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"csi0_ahb",
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"csi0",
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"csi0_phy",
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"csi0_pix",
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"csi0_rdi",
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"csi1_ahb",
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"csi1",
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"csi1_phy",
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"csi1_pix",
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"csi1_rdi",
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"csi2_ahb",
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"csi2",
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"csi2_phy",
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"csi2_pix",
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"csi2_rdi",
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"ahb",
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"vfe0",
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"csi_vfe0",
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"vfe_ahb",
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"vfe_axi";
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iommus = <&apps_iommu 3>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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};
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};
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};
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cci: cci@1b0c000 {
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compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x01b0c000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
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clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
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<&gcc GCC_CAMSS_TOP_AHB_CLK>,
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<&gcc GCC_CAMSS_CCI_AHB_CLK>,
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<&gcc GCC_CAMSS_CCI_CLK>,
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<&gcc GCC_CAMSS_AHB_CLK>;
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clock-names = "ispif_ahb",
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"camss_top_ahb",
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"cci_ahb",
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"cci",
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"camss_ahb";
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assigned-clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
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<&gcc GCC_CAMSS_CCI_CLK>;
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assigned-clock-rates = <80000000>,
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<19200000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cci0_default>;
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status = "disabled";
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cci_i2c0: i2c-bus@0 {
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reg = <0>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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gpu: gpu@1c00000 {
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compatible = "qcom,adreno-405.0", "qcom,adreno";
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reg = <0x01c00000 0x10000>;
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#iommu-cells = <1>;
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qcom,iommu-secure-id = <17>;
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/* vfe */
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iommu-ctx@3000 {
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compatible = "qcom,msm-iommu-v1-sec";
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reg = <0x3000 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* mdp_0: */
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iommu-ctx@4000 {
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compatible = "qcom,msm-iommu-v1-ns";

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