@@ -68,11 +68,18 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
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* - Processors with Cortex-A75 cores
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* - Processors with Cortex-A76 cores
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* - Processors with Cortex-A77 cores
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+ * - Processors with Cortex-A78 cores
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+ * - Processors with Cortex-A510 cores
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+ * - Processors with Cortex-A710 cores
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+ * - Processors with Cortex-A715 cores
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+ * - Processors with Cortex-X1 cores
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+ * - Processors with Cortex-X2 cores
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+ * - Processors with Cortex-X3 cores
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* - Processors with Exynos M4 cores
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* - Processors with Exynos M5 cores
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* - Neoverse N1 cores
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- * - Neoverse V1 cores
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* - Neoverse N2 cores
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+ * - Neoverse V1 cores
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*/
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if (chipset -> series == cpuinfo_arm_chipset_series_samsung_exynos && chipset -> model == 9810 ) {
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/* Only little cores of Exynos 9810 support FP16 & RDM */
@@ -83,11 +90,18 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
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case UINT32_C (0x4100D060 ): /* Cortex-A65 */
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case UINT32_C (0x4100D0A0 ): /* Cortex-A75 */
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case UINT32_C (0x4100D0B0 ): /* Cortex-A76 */
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+ case UINT32_C (0x4100D0C0 ): /* Neoverse N1 */
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case UINT32_C (0x4100D0D0 ): /* Cortex-A77 */
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case UINT32_C (0x4100D0E0 ): /* Cortex-A76AE */
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+ case UINT32_C (0x4100D400 ): /* Neoverse V1 */
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+ case UINT32_C (0x4100D410 ): /* Cortex-A78 */
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+ case UINT32_C (0x4100D440 ): /* Cortex-X1 */
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case UINT32_C (0x4100D460 ): /* Cortex-A510 */
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case UINT32_C (0x4100D470 ): /* Cortex-A710 */
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case UINT32_C (0x4100D480 ): /* Cortex-X2 */
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+ case UINT32_C (0x4100D490 ): /* Neoverse N2 */
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+ case UINT32_C (0x4100D4D0 ): /* Cortex-A715 */
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+ case UINT32_C (0x4100D4E0 ): /* Cortex-X3 */
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case UINT32_C (0x4800D400 ): /* Cortex-A76 (HiSilicon) */
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case UINT32_C (0x51008020 ): /* Kryo 385 Gold (Cortex-A75) */
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case UINT32_C (0x51008030 ): /* Kryo 385 Silver (Cortex-A55) */
@@ -103,20 +117,43 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo(
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/*
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* NEON VDOT instructions are not indicated in /proc/cpuinfo.
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- * Use a MIDR-based heuristic to whitelist processors known to support it.
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+ * Use a MIDR-based heuristic to whitelist processors known to support it:
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+ * - Processors with Cortex-A65 cores
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+ * - Processors with Cortex-A76 cores
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+ * - Processors with Cortex-A77 cores
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+ * - Processors with Cortex-A78 cores
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+ * - Processors with Cortex-A510 cores
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+ * - Processors with Cortex-A710 cores
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+ * - Processors with Cortex-A715 cores
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+ * - Processors with Cortex-X1 cores
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+ * - Processors with Cortex-X2 cores
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+ * - Processors with Cortex-X3 cores
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+ * - Processors with Exynos M4 cores
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+ * - Processors with Exynos M5 cores
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+ * - Neoverse N1 cores
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+ * - Neoverse N2 cores
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+ * - Neoverse V1 cores
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*/
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switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK )) {
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+ case UINT32_C (0x4100D060 ): /* Cortex-A65 */
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case UINT32_C (0x4100D0B0 ): /* Cortex-A76 */
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+ case UINT32_C (0x4100D0C0 ): /* Neoverse N1 */
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case UINT32_C (0x4100D0D0 ): /* Cortex-A77 */
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case UINT32_C (0x4100D0E0 ): /* Cortex-A76AE */
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- case UINT32_C (0x4800D400 ): /* Cortex-A76 (HiSilicon) */
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+ case UINT32_C (0x4100D400 ): /* Neoverse V1 */
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+ case UINT32_C (0x4100D410 ): /* Cortex-A78 */
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+ case UINT32_C (0x4100D440 ): /* Cortex-X1 */
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case UINT32_C (0x4100D460 ): /* Cortex-A510 */
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case UINT32_C (0x4100D470 ): /* Cortex-A710 */
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case UINT32_C (0x4100D480 ): /* Cortex-X2 */
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+ case UINT32_C (0x4100D490 ): /* Neoverse N2 */
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+ case UINT32_C (0x4100D4D0 ): /* Cortex-A715 */
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+ case UINT32_C (0x4100D4E0 ): /* Cortex-X3 */
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+ case UINT32_C (0x4800D400 ): /* Cortex-A76 (HiSilicon) */
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case UINT32_C (0x51008040 ): /* Kryo 485 Gold (Cortex-A76) */
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case UINT32_C (0x51008050 ): /* Kryo 485 Silver (Cortex-A55) */
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- case UINT32_C (0x53000030 ): /* Exynos- M4 */
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- case UINT32_C (0x53000040 ): /* Exynos- M5 */
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+ case UINT32_C (0x53000030 ): /* Exynos M4 */
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+ case UINT32_C (0x53000040 ): /* Exynos M5 */
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isa -> dot = true;
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break ;
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case UINT32_C (0x4100D050 ): /* Cortex A55: revision 1 or later only */
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