Remove unused aievec dialect ops (#1279)

We can add these back as/when we need them, from mlir-aie

Author: newling

compiler/plugins/target/AMD-AIE/aievec/AIEVecOps.cpp

@@ -420,191 +420,6 @@ LogicalResult ShuffleOp::verify() {
   return success();
 }
 
-//===----------------------------------------------------------------------===//
-// MulElemOp and FMAElemOp
-//===----------------------------------------------------------------------===//
-
-// MulElemOp and FMAElemOp are structurally similar, except that FMAElem op
-// has few extra fields (accumulator, bool flag to indicate if it is fmsub,
-// etc.). We create some specializations to print those fields specifically for
-// FMAElemOp and MULElemOp.
-
-// Print the accumulator
-template <typename T>
-void printAccumulator(OpAsmPrinter &p, T op);
-template <>
-inline void printAccumulator(OpAsmPrinter &p, aievec::FMAElemOp op) {
-  p << ", " << op.getAcc();
-}
-template <>
-inline void printAccumulator(OpAsmPrinter &p, aievec::MulElemOp op) {}
-
-// Mark fmsub indicator as elided if the FMAElem op is not fmsub
-template <typename T>
-void elideFMSubAttr(T op, SmallVector<StringRef, 4> &elidedAttrs);
-template <>
-inline void elideFMSubAttr(aievec::FMAElemOp op,
-                           SmallVector<StringRef, 4> &elidedAttrs) {
-  if (!op.getFmsub()) elidedAttrs.push_back(op.getSubAttrName());
-}
-
-template <>
-inline void elideFMSubAttr(aievec::MulElemOp op,
-                           SmallVector<StringRef, 4> &elidedAttrs) {}
-
-// Print out MulElem and FMAElem op.
-template <typename T>
-static void printMulFMAElemOp(OpAsmPrinter &p, T op) {
-  // Print the left operand
-  p << " " << op.getLhs();
-  // Print the right operand
-  p << ", " << op.getRhs();
-  // For fma op, print the accumulator
-  printAccumulator(p, op);
-
-  // Print the attributes, but don't print attributes that are empty strings
-  SmallVector<StringRef, 4> elidedAttrs;
-  for (int idx = 0; idx < 2; ++idx) {
-    elideFMSubAttr(op, elidedAttrs);
-  }
-  p.printOptionalAttrDict(op->getAttrs(), elidedAttrs);
-
-  // And now print the types
-  p << " : " << op.getLhs().getType() << ", " << op.getRhs().getType();
-  p << ", " << op.getResult().getType();
-}
-
-void MulElemOp::print(OpAsmPrinter &p) {
-  printMulFMAElemOp<aievec::MulElemOp>(p, *this);
-}
-
-void aievec::FMAElemOp::print(OpAsmPrinter &p) {
-  printMulFMAElemOp<aievec::FMAElemOp>(p, *this);
-}
-
-// Verify MulElem and FMAElem op.
-template <typename T>
-LogicalResult verifyMulFMAElemOp(T op) {
-  // Verify the types
-  auto lhsType = llvm::dyn_cast<VectorType>(op.getLhs().getType());
-  auto rhsType = llvm::dyn_cast<VectorType>(op.getRhs().getType());
-
-  if (!lhsType || !rhsType) return op.emitError("requires vector type");
-
-  auto resultType = llvm::dyn_cast<VectorType>(op.getResult().getType());
-
-  if (!resultType) return op.emitError("requires vector type");
-
-  // Additional checks for FMAElem op
-  // Get the width of the underlying scalars of all the vectors
-  Type ltype = lhsType.getElementType();
-  Type rtype = rhsType.getElementType();
-  Type atype = resultType.getElementType();
-  unsigned ltypeWidth = ltype.getIntOrFloatBitWidth();
-  unsigned rtypeWidth = rtype.getIntOrFloatBitWidth();
-  unsigned atypeWidth = atype.getIntOrFloatBitWidth();
-
-  // Checks on the number of lanes
-  unsigned rhsLanes = getVectorLaneSize(rhsType);
-  unsigned lhsLanes = getVectorLaneSize(lhsType);
-
-  // lane size must match
-  if (lhsLanes != rhsLanes) {
-    return op.emitError(
-        "The number of lanes in lhs operand "
-        "must be the same as rhs operand");
-  }
-
-  // lhs and rhs vector's element type must match
-  if (ltype != rtype)
-    return op.emitError(
-        "The element type of lhs and rhs "
-        "operand vectors must match");
-
-  // The integer datatype of accumulator must always be greater width
-  if (isa<IntegerType>(atype)) {
-    if (!isa<IntegerType>(ltype))
-      return op.emitError("Integer result must have integer operands");
-
-    if (ltypeWidth >= atypeWidth || rtypeWidth >= atypeWidth)
-      return op.emitError(
-          "the element type of accumulator must have "
-          "wider width than that of the operand vectors");
-  } else if (isa<FloatType>(atype)) {
-    if (!isa<FloatType>(ltype))
-      return op.emitError(
-          "Floating point result must have "
-          "floating point operands");
-  }
-
-  return success();
-}
-
-LogicalResult aievec::MulElemOp::verify() {
-  return verifyMulFMAElemOp<aievec::MulElemOp>(*this);
-}
-
-LogicalResult aievec::FMAElemOp::verify() {
-  return verifyMulFMAElemOp<aievec::FMAElemOp>(*this);
-}
-
-// Parse MulElem and FMAElem op.
-ParseResult parseMulFMAElemOp(OpAsmParser &parser, OperationState &result,
-                              bool isFMAElemOp = true) {
-  llvm::SMLoc typesLoc;
-  SmallVector<Type, 3> types;
-  OpAsmParser::UnresolvedOperand lhs, rhs, acc;
-
-  // Parse the lhs and rhs
-  if (parser.parseOperand(lhs) || parser.parseComma() ||
-      parser.parseOperand(rhs))
-    return failure();
-
-  // Parse the acc for FMA op
-  if (isFMAElemOp) {
-    if (parser.parseComma() || parser.parseOperand(acc)) return failure();
-  }
-
-  // Parse all the attributes and types
-  if (parser.parseOptionalAttrDict(result.attributes) ||
-      parser.getCurrentLocation(&typesLoc) || parser.parseColonTypeList(types))
-    return failure();
-
-  // Assert that there are three types: lhs, rhs, and acc
-  if (types.size() != 3)
-    return parser.emitError(typesLoc, "requires three types");
-
-  // Some verification
-  VectorType lhsType = llvm::dyn_cast<VectorType>(types[0]);
-  if (!lhsType) return parser.emitError(typesLoc, "requires vector type");
-  VectorType rhsType = llvm::dyn_cast<VectorType>(types[1]);
-  if (!rhsType) return parser.emitError(typesLoc, "requires vector type");
-
-  // Int ops use the accumulator while float ops use normal vector registers
-  VectorType accType = llvm::dyn_cast<VectorType>(types[2]);
-  if (!accType) return parser.emitError(typesLoc, "requires vector type");
-
-  // Populate the lhs and rhs operands, and result
-  if (parser.resolveOperand(lhs, lhsType, result.operands) ||
-      parser.resolveOperand(rhs, rhsType, result.operands))
-    return failure();
-
-  // Populate acc operand for FMA op
-  if (isFMAElemOp) {
-    if (parser.resolveOperand(acc, accType, result.operands)) return failure();
-  }
-
-  return parser.addTypeToList(accType, result.types);
-}
-
-ParseResult MulElemOp::parse(OpAsmParser &parser, OperationState &result) {
-  return parseMulFMAElemOp(parser, result, false);
-}
-
-ParseResult FMAElemOp::parse(OpAsmParser &parser, OperationState &result) {
-  return parseMulFMAElemOp(parser, result, true);
-}
-
 //===----------------------------------------------------------------------===//
 // ExtOp
 //===----------------------------------------------------------------------===//

compiler/plugins/target/AMD-AIE/aievec/AIEVecOps.td

@@ -318,60 +318,4 @@ def AIEVec_ShuffleOp : AIEVec_Op<"shuffle",
   let hasVerifier = 1;
 }
 
-def AIEVec_MulElemOp:
-  AIEVec_Op<"mul_elem", [
-    Pure,
-    SameTypeOperands,
-    SameOperandsShape,
-    SameOperandsAndResultShape,
-    isOperandResultTypePairValidForAIE2MulElem<"lhs", "rhs", "result">
-  ]>,
-  Arguments<(ins
-    VectorOfLengthAndType<[16, 32], [I8, I16, I32, BF16, F32]>:$lhs,
-    VectorOfLengthAndType<[16, 32], [I8, I16, I32, BF16, F32]>:$rhs)>,
-  Results<(outs
-    VectorOfLengthAndType<[16, 32], [I32, I64, F32]>:$result)> {
-  let summary = "AIE2 vector element-wise multiply";
-  let description = [{
-    AMD-specific multiply operation that multiplies two 1-D vectors in the same channel.
-    The vector sizes are at least 512 bits.
-    `$result = `$lhs * $rhs`.
-    Currently, the following are the supported type combinations:
-        lhs                | rhs                | Accumulator
-      :------------------:|:------------------:|:-----------------:
-        `vector<32xi8>`    | `vector<32xi8>`    | `vector<32xi32>`
-        `vector<32xi16>`   | `vector<32xi16>`   | `vector<32xi32>`
-        `vector<16xi32>`   | `vector<16xi32>`   | `vector<16xi64>`
-        `vector<16xbf16>`  | `vector<16xbf16>`  | `vector<16xf32>`
-        `vector<16xf32>`   | `vector<16xf32>`   | `vector<16xf32>`'
-  }];
-}
-
-def AIEVec_FMAElemOp :
-  AIEVec_Op<"mac_elem", [
-    Pure
-  ]>,
-  Arguments<(ins AnyVectorOfNonZeroRank:$lhs, AnyVectorOfNonZeroRank:$rhs, AnyVectorOfNonZeroRank:$acc,
-               DefaultValuedAttr<BoolAttr, "false">:$fmsub)>,
-  Results<(outs AnyVectorOfNonZeroRank:$result)> {
-  let summary = "AIE2 element-wise vector fused multiply-add";
-  let description = [{
-    AMD-specific multiply-add operation. It multiplies two 1-D vectors in the same channel,
-    and adds the result to an accumulator.
-    `$result = `$lhs * $rhs + $acc`.
-    Note: the same operator can be used as fmsub operator by setting the
-    'fmsub' bool to true.
-  }];
-  let builders = [
-    OpBuilder<(ins "mlir::Value":$lhs, "mlir::Value":$rhs, "mlir::Value":$acc,
-            "bool":$fmsub),
-    [{build($_builder, $_state, acc.getType(), lhs, rhs, acc,
-            fmsub);}]>
-  ];
-  let extraClassDeclaration = [{
-    // Get the attribute names
-    llvm::StringRef getSubAttrName() { return "fmsub"; }
-  }];
-}
-
 #endif // AIEVEC_OPS

compiler/plugins/target/AMD-AIE/aievec/AIEVecToLLVM.cpp

@@ -611,66 +611,6 @@ class SRSOpConversion : public mlir::ConvertOpToLLVMPattern<aievec::SRSOp> {
   }
 };
 
-class FMAElemOpConversion
-    : public mlir::ConvertOpToLLVMPattern<aievec::FMAElemOp> {
- public:
-  using ConvertOpToLLVMPattern<aievec::FMAElemOp>::ConvertOpToLLVMPattern;
-
- public:
-  FMAElemOpConversion(LLVMTypeConverter &converter, AMDAIE::AMDAIEDevice device)
-      : mlir::ConvertOpToLLVMPattern<aievec::FMAElemOp>(converter),
-        device(device) {}
-
- private:
-  AMDAIE::AMDAIEDevice device;
-
-  LogicalResult matchAndRewrite(
-      aievec::FMAElemOp fmaOp, OpAdaptor adaptor,
-      ConversionPatternRewriter &rewriter) const override {
-    assert(AMDAIE::isAie2(device) && "FMAElemOp currently only supports AIE2.");
-    auto loc = fmaOp.getLoc();
-    auto lhs = adaptor.getLhs();
-    auto rhs = adaptor.getRhs();
-    auto acc = adaptor.getAcc();
-    auto lhsTy = cast<VectorType>(lhs.getType());
-    auto rhsTy = cast<VectorType>(rhs.getType());
-    auto accTy = cast<VectorType>(acc.getType());
-    auto flatLhsTy = getFlattenedVectorType(lhsTy);
-    auto flatRhsTy = getFlattenedVectorType(rhsTy);
-    auto flatAccTy = getFlattenedVectorType(accTy);
-
-    // Flatten operands, if needed
-    if (lhsTy != flatLhsTy)
-      lhs = rewriter.create<vector::ShapeCastOp>(loc, flatLhsTy, lhs);
-    if (rhsTy != flatRhsTy)
-      rhs = rewriter.create<vector::ShapeCastOp>(loc, flatRhsTy, rhs);
-    if (accTy != flatAccTy)
-      acc = rewriter.create<vector::ShapeCastOp>(loc, flatAccTy, acc);
-
-    Type i32ty = rewriter.getI32Type();
-    auto confCst = rewriter.create<LLVM::ConstantOp>(
-        loc, i32ty,
-        rewriter.getI32IntegerAttr(DataPathConfiguration(
-                                       /*xSigned=*/0, /*ySigned=*/0,
-                                       /*aMode=*/2, /*bMode=*/3,
-                                       /*cMode=*/1)
-                                       .get()));
-
-    auto macIntrOp =
-        forceCastOperandsAndCreateTarget<xllvm::AIEVec2MacConfBF16IntrOp>(
-            rewriter, loc, {lhs, rhs, acc, confCst});
-
-    // Recast/Reshape result
-    auto resVal =
-        forceCastValueToType(rewriter, loc, macIntrOp.getResult(), flatAccTy);
-    if (flatAccTy != accTy)
-      resVal = rewriter.create<vector::ShapeCastOp>(loc, accTy, resVal);
-
-    rewriter.replaceOp(fmaOp, resVal);
-    return success();
-  }
-};
-
 class MatMulOpConversion
     : public mlir::ConvertOpToLLVMPattern<aievec::MatMulOp> {
   using ConvertOpToLLVMPattern<aievec::MatMulOp>::ConvertOpToLLVMPattern;
@@ -1043,9 +983,8 @@ struct ConvertAIEVecToLLVMPass
         [&](VectorType type) -> std::optional<Type> { return type; });
 
     patterns.add<UPSOpConversion, SRSOpConversion, FoldAIECastOps,
-                 FMAElemOpConversion, ShuffleOpConversion, ExtOpConversion,
-                 ShiftOpConversion, MatMulOpConversion>(converter,
-                                                        maybeDevice.value());
+                 ShuffleOpConversion, ExtOpConversion, ShiftOpConversion,
+                 MatMulOpConversion>(converter, maybeDevice.value());
 
     LLVMConversionTarget target(getContext());
 

compiler/plugins/target/AMD-AIE/aievec/AIEVecTypeConstraints.td

@@ -66,15 +66,4 @@ class VectorTypesMatch<string op1, Type t1,
        SubstLeaves<"$_self", VectorType<op2>.result, t2.predicate>,
        SubstLeaves<"$_self", VectorType<op3>.result, t3.predicate>]>;
 
-class isOperandResultTypePairValidForAIE2MulElem<string lhs, string rhs, string acc> :
-  PredOpTrait<acc # " type is a valid accumulator type given the type of the" #
-              " operands.",
-    Or<[
-      And <[ElementTypeIsPred<acc,I32>, ElementTypeIsPred<lhs,I8>]>,
-      And <[ElementTypeIsPred<acc,I32>, ElementTypeIsPred<lhs,I16>]>,
-      And <[ElementTypeIsPred<acc,I64>, ElementTypeIsPred<lhs,I32>]>,
-      And <[ElementTypeIsPred<acc,F32>, ElementTypeIsPred<lhs,BF16>]>,
-      And <[ElementTypeIsPred<acc,F32>, ElementTypeIsPred<lhs,F32>]>
-    ]>>;
-
 #endif