style: format hex literals as lowercase

Author: mkroening

rustfmt.toml

@@ -1,3 +1,4 @@
 group_imports = "StdExternalCrate"
 hard_tabs = true
+hex_literal_case = "Lower"
 imports_granularity = "Module"

src/arch/aarch64/kernel/interrupts.rs

@@ -175,7 +175,7 @@ pub(crate) extern "C" fn do_sync(state: &State) {
 	let irqid = GicV3::get_and_acknowledge_interrupt().unwrap();
 	let esr = ESR_EL1.get();
 	let ec = esr >> 26;
-	let iss = esr & 0x00FF_FFFF;
+	let iss = esr & 0x00ff_ffff;
 	let pc = ELR_EL1.get();
 
 	/* data abort from lower or current level */

src/arch/aarch64/kernel/pci.rs

@@ -25,19 +25,19 @@ pub(crate) struct PciConfigRegion(VirtAddr);
 impl PciConfigRegion {
 	pub const fn new(addr: VirtAddr) -> Self {
 		assert!(
-			addr.as_u64() & 0x0FFF_FFFF == 0,
+			addr.as_u64() & 0x0fff_ffff == 0,
 			"Unaligned PCI Config Space"
 		);
 		Self(addr)
 	}
 
 	#[inline]
 	fn addr_from_offset(&self, pci_addr: PciAddress, offset: u16) -> usize {
-		assert!(offset & 0xF000 == 0, "Invalid offset");
+		assert!(offset & 0xf000 == 0, "Invalid offset");
 		(u64::from(pci_addr.bus()) << 20
 			| u64::from(pci_addr.device()) << 15
 			| u64::from(pci_addr.function()) << 12
-			| (u64::from(offset) & 0xFFF)
+			| (u64::from(offset) & 0xfff)
 			| self.0.as_u64()) as usize
 	}
 }

src/arch/aarch64/kernel/processor.rs

@@ -72,7 +72,7 @@ impl CpuFrequency {
 	}
 
 	unsafe fn detect_from_register(&mut self) -> Result<(), ()> {
-		let hz = CNTFRQ_EL0.get() & 0xFFFF_FFFF;
+		let hz = CNTFRQ_EL0.get() & 0xffff_ffff;
 		self.set_detected_cpu_frequency(hz.try_into().unwrap(), CpuFrequencySources::Register)
 	}
 

src/arch/aarch64/kernel/scheduler.rs

@@ -354,7 +354,7 @@ impl TaskFrame for Task {
 			// Set a marker for debugging at the very top.
 			let mut stack = self.stacks.get_kernel_stack() + self.stacks.get_kernel_stack_size()
 				- TaskStacks::MARKER_SIZE;
-			*stack.as_mut_ptr::<u64>() = 0xDEAD_BEEFu64;
+			*stack.as_mut_ptr::<u64>() = 0xdead_beefu64;
 
 			// Put the State structure expected by the ASM switch() function on the stack.
 			stack -= mem::size_of::<State>();
@@ -374,7 +374,7 @@ impl TaskFrame for Task {
 			(*state).spsel = 1;
 
 			/* Zero the condition flags. */
-			(*state).spsr_el1 = 0x3E5;
+			(*state).spsr_el1 = 0x3e5;
 
 			// Set the task's stack pointer entry to the stack we have just crafted.
 			self.last_stack_pointer = stack;
@@ -383,7 +383,7 @@ impl TaskFrame for Task {
 			self.user_stack_pointer = self.stacks.get_user_stack()
 				+ self.stacks.get_user_stack_size()
 				- TaskStacks::MARKER_SIZE;
-			*self.user_stack_pointer.as_mut_ptr::<u64>() = 0xDEAD_BEEFu64;
+			*self.user_stack_pointer.as_mut_ptr::<u64>() = 0xdead_beefu64;
 			(*state).sp_el0 = self.user_stack_pointer.as_u64();
 		}
 	}

src/arch/aarch64/mm/paging.rs

@@ -16,7 +16,7 @@ use crate::{mm, scheduler, KERNEL_STACK_SIZE};
 /// Setting the upper bits to zero tells the MMU to use TTBR0 for the base address for the first table.
 ///
 /// See entry.S and ARM Cortex-A Series Programmer's Guide for ARMv8-A, Version 1.0, PDF page 172
-const L0TABLE_ADDRESS: VirtAddr = VirtAddr::new(0x0000_FFFF_FFFF_F000u64);
+const L0TABLE_ADDRESS: VirtAddr = VirtAddr::new(0x0000_ffff_ffff_f000u64);
 
 /// Number of Offset bits of a virtual address for a 4 KiB page, which are shifted away to get its Page Frame Number (PFN).
 const PAGE_BITS: usize = 12;
@@ -25,7 +25,7 @@ const PAGE_BITS: usize = 12;
 const PAGE_MAP_BITS: usize = 9;
 
 /// A mask where PAGE_MAP_BITS are set to calculate a table index.
-const PAGE_MAP_MASK: usize = 0x1FF;
+const PAGE_MAP_MASK: usize = 0x1ff;
 
 bitflags! {
 	/// Useful flags for an entry in either table (L0Table, L1Table, L2Table, L3Table).

src/arch/riscv64/kernel/scheduler.rs

@@ -385,7 +385,7 @@ impl TaskFrame for Task {
 			// Set a marker for debugging at the very top.
 			let mut stack =
 				self.stacks.get_kernel_stack() + self.stacks.get_kernel_stack_size() - 0x10u64;
-			*stack.as_mut_ptr::<u64>() = 0xDEAD_BEEFu64;
+			*stack.as_mut_ptr::<u64>() = 0xdead_beefu64;
 
 			// Put the State structure expected by the ASM switch() function on the stack.
 			stack -= mem::size_of::<State>();

src/arch/riscv64/mm/paging.rs

@@ -19,7 +19,7 @@ const PAGE_BITS: usize = 12;
 const PAGE_MAP_BITS: usize = 9;
 
 /// A mask where PAGE_MAP_BITS are set to calculate a table index.
-const PAGE_MAP_MASK: usize = 0x1FF;
+const PAGE_MAP_MASK: usize = 0x1ff;
 
 /// Number of page levels
 const PAGE_LEVELS: usize = 3;
@@ -104,7 +104,7 @@ impl PageTableEntry {
 	pub fn address(&self) -> PhysAddr {
 		PhysAddr::new(
 			(
-				self.physical_address_and_flags.as_u64() & !(0x3FFu64)
+				self.physical_address_and_flags.as_u64() & !(0x3ffu64)
 				//& !(0x3FFu64 << 54)
 			) << 2,
 		)

src/arch/x86_64/kernel/acpi.rs

@@ -13,15 +13,15 @@ use crate::arch::x86_64::mm::{paging, virtualmem};
 use crate::env;
 
 /// Memory at this physical address is supposed to contain a pointer to the Extended BIOS Data Area (EBDA).
-const EBDA_PTR_LOCATION: PhysAddr = PhysAddr::new(0x0000_040E);
+const EBDA_PTR_LOCATION: PhysAddr = PhysAddr::new(0x0000_040e);
 /// Minimum physical address where a valid EBDA must be located.
 const EBDA_MINIMUM_ADDRESS: PhysAddr = PhysAddr::new(0x400);
 /// The size of the EBDA window that is searched for an ACPI RSDP.
 const EBDA_WINDOW_SIZE: usize = 1024;
 /// The lower bound of the other address range, where the ACPI RSDP could be located.
-const RSDP_SEARCH_ADDRESS_LOW: PhysAddr = PhysAddr::new(0xE_0000);
+const RSDP_SEARCH_ADDRESS_LOW: PhysAddr = PhysAddr::new(0xe_0000);
 /// The upper bound of the other address range, where the ACPI RSDP could be located.
-const RSDP_SEARCH_ADDRESS_HIGH: PhysAddr = PhysAddr::new(0xF_FFFF);
+const RSDP_SEARCH_ADDRESS_HIGH: PhysAddr = PhysAddr::new(0xf_ffff);
 /// Length in bytes of the structure, over which the basic (ACPI 1.0) checksum is calculated.
 const RSDP_CHECKSUM_LENGTH: usize = 20;
 /// Length in byte sof the structure, over which the extended (ACPI 2.0+) checksum is calculated.
@@ -36,7 +36,7 @@ const AML_ZEROOP: u8 = 0x00;
 /// ACPI AML opcode indicating a single one byte as the data.
 const AML_ONEOP: u8 = 0x01;
 /// ACPI AML opcode indicating that a single byte with the data follows.
-const AML_BYTEPREFIX: u8 = 0x0A;
+const AML_BYTEPREFIX: u8 = 0x0a;
 
 /// Bit to enable an ACPI Sleep State.
 const SLP_EN: u16 = 1 << 13;

src/arch/x86_64/kernel/apic.rs

@@ -369,11 +369,11 @@ fn search_mp_floating(memory_range: AddrRange<PhysAddr>) -> Result<&'static Apic
 /// Helper function to detect APIC by the Multiprocessor Specification
 fn detect_from_mp() -> Result<PhysAddr, ()> {
 	let mp_float = if let Ok(mpf) = search_mp_floating(
-		AddrRange::new(PhysAddr::new(0x9F000u64), PhysAddr::new(0xA0000u64)).unwrap(),
+		AddrRange::new(PhysAddr::new(0x9f000u64), PhysAddr::new(0xa0000u64)).unwrap(),
 	) {
 		Ok(mpf)
 	} else if let Ok(mpf) = search_mp_floating(
-		AddrRange::new(PhysAddr::new(0xF0000u64), PhysAddr::new(0x10_0000u64)).unwrap(),
+		AddrRange::new(PhysAddr::new(0xf0000u64), PhysAddr::new(0x10_0000u64)).unwrap(),
 	) {
 		Ok(mpf)
 	} else {
@@ -415,7 +415,7 @@ fn detect_from_mp() -> Result<PhysAddr, ()> {
 
 	if mp_config.entry_count == 0 {
 		warn!("No MP table entries! Guess IO-APIC!");
-		let default_address = PhysAddr::new(0xFEC0_0000);
+		let default_address = PhysAddr::new(0xfec0_0000);
 
 		init_ioapic_address(default_address);
 	} else {
@@ -455,7 +455,7 @@ fn detect_from_mp() -> Result<PhysAddr, ()> {
 fn default_apic() -> PhysAddr {
 	warn!("Try to use default APIC address");
 
-	let default_address = PhysAddr::new(0xFEE0_0000);
+	let default_address = PhysAddr::new(0xfee0_0000);
 
 	// currently, uhyve doesn't support an IO-APIC
 	if !env::is_uhyve() {
@@ -866,7 +866,7 @@ pub fn wakeup_core(core_id_to_wakeup: CoreId) {
 /// Translate the x2APIC MSR into an xAPIC memory address.
 #[inline]
 fn translate_x2apic_msr_to_xapic_address(x2apic_msr: u32) -> VirtAddr {
-	*LOCAL_APIC_ADDRESS.get().unwrap() + ((u64::from(x2apic_msr) & 0xFF) << 4)
+	*LOCAL_APIC_ADDRESS.get().unwrap() + ((u64::from(x2apic_msr) & 0xff) << 4)
 }
 
 fn local_apic_read(x2apic_msr: u32) -> u32 {
@@ -902,11 +902,11 @@ fn ioapic_read(reg: u32) -> u32 {
 }
 
 fn ioapic_version() -> u32 {
-	ioapic_read(IOAPIC_REG_VER) & 0xFF
+	ioapic_read(IOAPIC_REG_VER) & 0xff
 }
 
 fn ioapic_max_redirection_entry() -> u8 {
-	((ioapic_read(IOAPIC_REG_VER) >> 16) & 0xFF) as u8
+	((ioapic_read(IOAPIC_REG_VER) >> 16) & 0xff) as u8
 }
 
 fn local_apic_write(x2apic_msr: u32, value: u64) {
@@ -934,7 +934,7 @@ fn local_apic_write(x2apic_msr: u32, value: u64) {
 
 			// Instead of a single 64-bit ICR register, xAPIC has two 32-bit registers (ICR1 and ICR2).
 			// There is a gap between them and the destination field in ICR2 is also 8 bits instead of 32 bits.
-			let destination = ((value >> 8) & 0xFF00_0000) as u32;
+			let destination = ((value >> 8) & 0xff00_0000) as u32;
 			let icr2 = unsafe {
 				&mut *((*LOCAL_APIC_ADDRESS.get().unwrap() + APIC_ICR2).as_mut_ptr::<u32>())
 			};

src/arch/x86_64/kernel/pci.rs

@@ -6,10 +6,10 @@ use crate::drivers::pci::{PciDevice, PCI_DEVICES};
 const PCI_MAX_BUS_NUMBER: u8 = 32;
 const PCI_MAX_DEVICE_NUMBER: u8 = 32;
 
-const PCI_CONFIG_ADDRESS_PORT: u16 = 0xCF8;
+const PCI_CONFIG_ADDRESS_PORT: u16 = 0xcf8;
 const PCI_CONFIG_ADDRESS_ENABLE: u32 = 1 << 31;
 
-const PCI_CONFIG_DATA_PORT: u16 = 0xCFC;
+const PCI_CONFIG_DATA_PORT: u16 = 0xcfc;
 
 #[derive(Debug, Copy, Clone)]
 pub(crate) struct PciConfigRegion;

src/arch/x86_64/kernel/pic.rs

@@ -7,8 +7,8 @@ use crate::scheduler;
 
 const PIC1_COMMAND_PORT: u16 = 0x20;
 const PIC1_DATA_PORT: u16 = 0x21;
-const PIC2_COMMAND_PORT: u16 = 0xA0;
-const PIC2_DATA_PORT: u16 = 0xA1;
+const PIC2_COMMAND_PORT: u16 = 0xa0;
+const PIC2_DATA_PORT: u16 = 0xa1;
 
 pub const PIC1_INTERRUPT_OFFSET: u8 = 32;
 const PIC2_INTERRUPT_OFFSET: u8 = 40;
@@ -69,8 +69,8 @@ pub fn init() {
 		outb(PIC2_DATA_PORT, 0x01);
 
 		// Mask all interrupts on both PICs.
-		outb(PIC1_DATA_PORT, 0xFF);
-		outb(PIC2_DATA_PORT, 0xFF);
+		outb(PIC1_DATA_PORT, 0xff);
+		outb(PIC2_DATA_PORT, 0xff);
 	}
 }
 

src/arch/x86_64/kernel/processor.rs

@@ -178,15 +178,15 @@ impl FPUState {
 			// Set FPU-related values to their default values after initialization.
 			// Refer to Intel Vol. 3A, Table 9-1. IA-32 and Intel 64 Processor States Following Power-up, Reset, or INIT
 			legacy_region: XSaveLegacyRegion {
-				fpu_control_word: 0x37F,
+				fpu_control_word: 0x37f,
 				fpu_status_word: 0,
-				fpu_tag_word: 0xFFFF,
+				fpu_tag_word: 0xffff,
 				fpu_opcode: 0,
 				fpu_instruction_pointer: 0,
 				fpu_instruction_pointer_high_or_cs: 0,
 				fpu_data_pointer: 0,
 				fpu_data_pointer_high_or_ds: 0,
-				mxcsr: 0x1F80,
+				mxcsr: 0x1f80,
 				mxcsr_mask: 0,
 				st_space: [0; 8 * 16],
 				xmm_space: [0; 16 * 16],
@@ -891,7 +891,7 @@ pub fn configure() {
 		} else {
 			panic!("Syscall support is missing");
 		}
-		wrmsr(IA32_STAR, (0x1Bu64 << 48) | (0x08u64 << 32));
+		wrmsr(IA32_STAR, (0x1bu64 << 48) | (0x08u64 << 32));
 		wrmsr(
 			IA32_LSTAR,
 			crate::arch::x86_64::kernel::syscall::syscall_handler as u64,

src/arch/x86_64/kernel/scheduler.rs

@@ -352,7 +352,7 @@ impl TaskFrame for Task {
 			// Set a marker for debugging at the very top.
 			let mut stack = self.stacks.get_kernel_stack() + self.stacks.get_kernel_stack_size()
 				- TaskStacks::MARKER_SIZE;
-			*stack.as_mut_ptr::<u64>() = 0xDEAD_BEEFu64;
+			*stack.as_mut_ptr::<u64>() = 0xdead_beefu64;
 
 			// Put the State structure expected by the ASM switch() function on the stack.
 			stack -= mem::size_of::<State>();

src/arch/x86_64/kernel/systemtime.rs

@@ -19,8 +19,8 @@ const CMOS_HOUR_REGISTER: u8 = 0x04;
 const CMOS_DAY_REGISTER: u8 = 0x07;
 const CMOS_MONTH_REGISTER: u8 = 0x08;
 const CMOS_YEAR_REGISTER: u8 = 0x09;
-const CMOS_STATUS_REGISTER_A: u8 = 0x0A;
-const CMOS_STATUS_REGISTER_B: u8 = 0x0B;
+const CMOS_STATUS_REGISTER_A: u8 = 0x0a;
+const CMOS_STATUS_REGISTER_B: u8 = 0x0b;
 
 const CMOS_UPDATE_IN_PROGRESS_FLAG: u8 = 1 << 7;
 const CMOS_24_HOUR_FORMAT_FLAG: u8 = 1 << 1;
@@ -52,7 +52,7 @@ impl Rtc {
 
 	/// Returns the binary value for a given value in BCD (Binary-Coded Decimal).
 	const fn convert_bcd_value(value: u8) -> u8 {
-		((value / 16) * 10) + (value & 0xF)
+		((value / 16) * 10) + (value & 0xf)
 	}
 
 	/// Returns the number of microseconds since the epoch from a given date.

src/arch/x86_64/kernel/vga.rs

@@ -5,16 +5,16 @@ use x86::io::*;
 use crate::arch::x86_64::mm::paging;
 use crate::arch::x86_64::mm::paging::{BasePageSize, PageTableEntryFlags, PageTableEntryFlagsExt};
 
-const CRT_CONTROLLER_ADDRESS_PORT: u16 = 0x3D4;
-const CRT_CONTROLLER_DATA_PORT: u16 = 0x3D5;
-const CURSOR_START_REGISTER: u8 = 0x0A;
+const CRT_CONTROLLER_ADDRESS_PORT: u16 = 0x3d4;
+const CRT_CONTROLLER_DATA_PORT: u16 = 0x3d5;
+const CURSOR_START_REGISTER: u8 = 0x0a;
 const CURSOR_DISABLE: u8 = 0x20;
 
 const ATTRIBUTE_BLACK: u8 = 0x00;
 const ATTRIBUTE_LIGHTGREY: u8 = 0x07;
 const COLS: usize = 80;
 const ROWS: usize = 25;
-const VGA_BUFFER_ADDRESS: PhysAddr = PhysAddr::new(0xB8000);
+const VGA_BUFFER_ADDRESS: PhysAddr = PhysAddr::new(0xb8000);
 
 static VGA_SCREEN: SpinMutex<VgaScreen> = SpinMutex::new(VgaScreen::new());
 

src/arch/x86_64/mm/paging.rs

@@ -94,7 +94,7 @@ pub use x86_64::structures::paging::{
 
 /// Returns a recursive page table mapping, its last entry is mapped to the table itself
 unsafe fn recursive_page_table() -> RecursivePageTable<'static> {
-	let level_4_table_addr = 0xFFFF_FFFF_FFFF_F000;
+	let level_4_table_addr = 0xffff_ffff_ffff_f000;
 	let level_4_table_ptr = ptr::with_exposed_provenance_mut(level_4_table_addr);
 	unsafe {
 		let level_4_table = &mut *(level_4_table_ptr);

src/arch/x86_64/mm/virtualmem.rs

@@ -162,7 +162,7 @@ pub fn print_information() {
 #[cfg(not(feature = "common-os"))]
 #[inline]
 pub const fn kernel_heap_end() -> VirtAddr {
-	VirtAddr::new(0x7FFF_FFFF_FFFFu64)
+	VirtAddr::new(0x7fff_ffff_ffffu64)
 }
 
 #[cfg(feature = "common-os")]

src/drivers/net/gem.rs

@@ -321,7 +321,7 @@ impl NetworkDriver for GEMDriver {
 				let word1_addr = self.rxbuffer_list + u64::from(index * 8 + 4);
 				let word1_entry =
 					unsafe { core::ptr::read_volatile(word1_addr.as_mut_ptr::<u32>()) };
-				let length = word1_entry & 0x1FFF;
+				let length = word1_entry & 0x1fff;
 				debug!("Received frame in buffer {}, length: {}", index, length);
 
 				// Starting point to search for next frame
@@ -347,7 +347,7 @@ impl NetworkDriver for GEMDriver {
 		if value {
 			// disable interrupts from the NIC
 			unsafe {
-				(*self.gem).int_disable.set(0x7FF_FEFF);
+				(*self.gem).int_disable.set(0x7ff_feff);
 			}
 		} else {
 			// Enable all known interrupts by setting the interrupt mask.
@@ -427,7 +427,7 @@ impl GEMDriver {
 			core::ptr::write_volatile(word1_addr.as_mut_ptr::<u32>(), 0);
 			// Give back ownership to GEM
 			let word0_entry = core::ptr::read_volatile(word0_addr.as_mut_ptr::<u32>());
-			core::ptr::write_volatile(word0_addr.as_mut_ptr::<u32>(), word0_entry & 0xFFFF_FFFE);
+			core::ptr::write_volatile(word0_addr.as_mut_ptr::<u32>(), word0_entry & 0xffff_fffe);
 		}
 	}
 
@@ -485,10 +485,10 @@ pub fn init_device(
 		// Clear the Statistics registers
 		(*gem).network_control.modify(NetworkControl::STATCLR::SET);
 		// Clear the status registers
-		(*gem).receive_status.set(0x0F);
-		(*gem).transmit_status.set(0x0F);
+		(*gem).receive_status.set(0x0f);
+		(*gem).transmit_status.set(0x0f);
 		// Disable all interrupts
-		(*gem).int_disable.set(0x7FF_FEFF);
+		(*gem).int_disable.set(0x7ff_feff);
 		// Clear the buffer queues
 		(*gem).rx_qbar.set(0x0);
 		(*gem).tx_qbar.set(0x0);
@@ -560,7 +560,7 @@ pub fn init_device(
 			warn! {"No PHY address provided. Trying to find PHY ..."}
 			for i in 0..32 {
 				match phy_read(gem, i, PhyReg::Control) {
-					0xFFFF => (), //Invalid
+					0xffff => (), //Invalid
 					0x0 => (),    //Invalid
 					_ => {
 						phy_addr = i;