How to use in Spartan 6? How to translate to Verilog?

[TheSonders]

I'm trying to use this code in a Spartan 6 board, however ISE14.7 does not support System Verilog.
Vivado supports SV but not Spartan 6 family :-(
I tried to translate this code to Verilog but packed assignaments like this get me confussed and don't know how to do it.
Any clue to translate it? Is there any tool to convert it to Verilog? Thanks.

logic [23:0] audio_sample_word_packet [3:0] [1:0];...

logic [23:0] audio_sample_word_buffer [1:0] [3:0] [1:0];...

audio_sample_word_packet <= audio_sample_word_buffer[!sample_buffer_current];

[sameer]

Hey, thanks for bringing this to my attention. I was not aware that SystemVerilog wouldn't work for Spartan 6. I'm most familiar with Quartus and Intel since that's what was available at my university, but I recently got a Spartan 7 to help test with 🙂 The project was originally in Verilog so it shouldn't be too much work to convert it back. The mixed packed/unpacked assignments look tricky. The best way to handle them is flattening i.e. [24*4*2-1:0] for audio sample word packet. I will look into some conversion tools to see if there's an option there. I can't revert all the projects under hdl-util back to Verilog, but since this is the most used project in the org it might be valuable to offer it as a legacy option. Though support for that would not be guaranteed in the long term. Will get back to you once I have more information.

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On Fri, Apr 2, 2021, at 00:01, Antonio Sanchez wrote: I'm trying to use this code in a Spartan 6 board, however ISE14.7 does not support System Verilog. Vivado supports SV but not Spartan 6 family :-( I tried to translate this code to Verilog but packed assignaments like this get me confussed and don't know how to do it. Any clue to translate it? Is there any tool to convert it to Verilog? Thanks. *logic [23:0] audio_sample_word_packet [3:0] [1:0];...* *logic [23:0] audio_sample_word_buffer [1:0] [3:0] [1:0];...* *audio_sample_word_packet <= audio_sample_word_buffer[!sample_buffer_current];* — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#24>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ACUVICA4KPM2VKWNR3XSGNDTGU6QFANCNFSM42IGXTWQ>.

[sameer]

Please give https://github.com/hdl-util/hdmi/tree/v1.2.1-verilog a try. I've converted to Verilog using sv2v and made sure it can compile.

Let me know if you run into any problems!

[TheSonders]

Thanks a lot! I'm on it right now!
After solving small issues (mixing of blocking and non-blocking assignments) and the problem of $clog2 in localparams...
I'm trying to solve the serializer (not posible in Verilog assign both on rise and fall edges)
Let's see if I can use the IP instantiated version of the SV code.

[sameer]

Cool, let me know how it goes!

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On Fri, Apr 2, 2021, at 20:56, Antonio Sanchez wrote: Thanks a lot! I'm on it right now! After solving small issues (mixing of blocking and non-blocking assignments) and the problem of $clog2 in localparams... I'm trying to solve the serializer (not posible in Verilog assign both on rise and fall edges) Let's see if I can use the IP instantiated version of the SV code. — You are receiving this because you were assigned. Reply to this email directly, view it on GitHub <#24 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ACUVICE2MRL5SEEUBHHL7F3TGZRUJANCNFSM42IGXTWQ>.

[TheSonders]

Sorry for taking so long. Bad news! I've tried several ways but can't get any HDMI image. I've solved som issues due the translation, and even used other serializers with the Spartan6 primitives.
As result: a few warnings, all signals routed, all constraints met, perfect timing report and bitfile created; but no image or sound.
I give up. Thanks a lot for your effort!

[sameer]

Hey, thanks for the update. That's really unfortunate. If you are willing to share the source I can try to debug things in simulation from my end.

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On Wed, Apr 21, 2021, at 05:56, Antonio Sanchez wrote: Sorry for taking so long. Bad news! I've tried several ways but can't get any HDMI image. I've solved som issues due the translation, and even used other serializers with the Spartan6 primitives. As result: a few warnings, all signals routed, all constraints met, perfect timing report and bitfile created; but no image or sound. I give up. Thanks a lot for your effort! — You are receiving this because you were assigned. Reply to this email directly, view it on GitHub <#24 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ACUVICBWWP2B7DUAFTKIFHLTJ2OMJANCNFSM42IGXTWQ>.

[TheSonders]

Sure! Thanks a lot!
https://github.com/TheSonders/Hdmi

[andykarpov]

Hey @sameer, @TheSonders!

Any updated since the last comment?
I'm also interesting in this project to be able to run on Spartan-6.
Thanks in advance!