Create a framework for adding address translation.

[BrentSeidel]

This should cover everything from direct physical access (no translation at all) through bank switching, simple address translation, all the way to sophisticated paged memory management units.

[BrentSeidel]

This may require creating a separate memory object and moving memory out of the simulator object. This would probably make simulations slightly slower, but would allow custom memory such as memory systems with holes and ways to signal to the simulator that memory is not present. This would also have to handle memory mapped I/O (perhaps all addressable I/O). The address translator would be inserted between the simulator and the memory.

This may be implemented by creating a new system object with the same (or similar) interface as a current simulator object. The system object would then contain a simulator (without memory), and address translator (possibly just pass-through), and a memory system object. This might also be a path to allowing multi-processor simulations.

[BrentSeidel]

This will also impact any I/O devices that use DMA.

[BrentSeidel]

Split simulators and I/O devices out of BBS.Sim_CPU into BBS.Sim_CPU.CPU and BBS.Sim_CPU.io packages (and sub-packages). Added a new BBS.Sim_CPU.bus package that should eventually the bus interface. The bus will be responsible for connecting the simulators with the I/O devices and memory (and possibly other simulators, but that comes much later).